Locality-conscious workload assignment for array-based computations in MPSOC architectures

While the past research discussed several advantages of multiprocessor-system-on-a-chip (MPSOC) architectures from both area utilization and design verification perspectives over complex single core based systems, compilation issues for these architectures have relatively received less attention. Programming MPSOCs can be challenging as several potentially conflicting issues such as data locality, parallelism and load balance across processors should be considered simultaneously. Most of the compilation techniques discussed in the literature for parallel architectures (not necessarily for MPSOCs) are loop based, i.e., they consider each loop nest in isolation. However, one key problem associated with such loop based techniques is that they fail to capture the interactions between the different loop nests in the application. This paper takes a more global approach to the problem and proposes a compilerdriven data locality optimization strategy in the context of embedded MPSOCs. An impo...

• Type: Conference
• Year: 2005
• Where: DAC
• Authors: Feihui Li, Mahmut T. Kandemir
• Keywords: DAC 2005, Design Automation, Keywords Data Locality, Loop Based Scheme, Loop Based Techniques