Incremental retiming for FPGA physical synthesis

In this paper, we present a new linear-time retiming algorithm that produces near-optimal results. Our implementation is specifically targeted at Altera's Stratix [1] FPGAbased designs, although the techniques described are general enough for any implementation medium. The algorithm is able to handle the architectural constraints of the target device, multiple timing constraints assigned by the user and implicit legality constraints. It ensures that register moves do not create asynchonous problems such as creating a glitch on a clock/reset signal. Categories and Subject Descriptors: B.6.3 [Logic Design]: Design Aids General Terms: Algorithms, Measurements, Experimentation, Theory

• Type: Conference
• Year: 2005
• Where: DAC
• Authors: Deshanand P. Singh, Valavan Manohararajah, Stephen Dean Brown
• Keywords: Architectural Constraints, DAC 2005, Design Automation, Implicit Legality Constraints, Multiple Timing Constraints