Cache coherence support for non-shared bus architecture on heterogeneous MPSoCs

We propose two novel integration techniques -- bypass and bookkeeping -- in the memory controller to address the cache coherence compatibility issue of a non-shared bus heterogeneous MPSoC. The bypass approach is an inexpensive and efficient solution for computation-bound applications while the bookkeeping approach eliminating unnecessary forwarding traffic offers an alternative for bandwidth-limited applications. Our RTOS kernel simulations show up to 6.65x speedup over the conventional software solution. Categories and Subject Descriptors C.3 [Computer Systems Organization]: Special-purpose and application-specific systems, Real-time and embedded systems General Terms Design Keywords Cache coherence, Inter-processor communication, Heterogeneous MPSoC, Real-time and embedded systems

• Type: Conference
• Year: 2005
• Where: DAC
• Authors: Taeweon Suh, Daehyun Kim, Hsien-Hsin S. Lee
• Keywords: Bus Heterogeneous Mpsoc, Cache Coherence Compatibility, DAC 2005, Design Automation, Keywords Cache Coherence