High Throughput and Low Cost Architecture for the Forward Quantization of the H.264/AVC Video Compression Standard

This work presents a dedicated hardware design for the Forward Quantization Module (Q module) of the H.264/AVC Video Coding Standard, using optimized multipliers. The goal of this design is to achieve high throughput rates combined with low hardware consumption. The architecture was described in VHDL and synthesized to the EP2S60F1020C3 Altera Stratix II FPGA and to the TSMC 0.18

• Type: Journal
• Year: 2010
• Where: CLEIEJ
• Authors: Felipe Sampaio, Daniel Palomino, Robson Dornelles, Luciano Volcan Agostini
• Keywords: Architecture, CLEIEJ 2010, Forward Quantization Module, Information Technology, Low Hardware Consumption