Design of low-power multiple constant multiplications using low-complexity minimum depth operations

Existing optimization algorithms for the multiplierless realization of multiple constant multiplications (MCM) typically target the minimization of the number of addition and subtraction operations. Since power dissipation is directly related to the amount of hardware, some power reduction is indirectly achieved by these algorithms. However, in many cases, glitching plays an equally important role in defining the power consumption. This is specially true for arithmetic circuits, and in particular to MCM due to high logic depth and large number of re-convergent paths. This paper introduces exact algorithms that search the optimal area of an MCM design at gate-level where each constant multiplication is implemented in its minimum depth. Experimental results show that the proposed algorithms lead to MCM designs consuming significantly less power with respect to those obtained by the MCM algorithms. Categories and Subject Descriptors B.2.0 [Arithmetic and Logic Structures]: General Gene...

• Type: Journal
• Year: 2011
• Where: GLVLSI
• Authors: Levent Aksoy, Eduardo Costa, Paulo F. Flores, José C. Monteiro
• Keywords: Algorithms, Constant Multiplications, GLVLSI 2011, Multiple Constant Multiplications, VLSI