A low-power implantable neuroprocessor on nano-FPGA for Brain Machine interface applications

This paper presents the implementation of a low-power and implantable neuroprocessor on low-cost nano-FPGA for data reduction and on-the-fly spike sorting in Brain Machine Interface applications. Detailed analysis of efficient utilization of the hardware resources, power consumption and design scalability are provided. The prototype we report here enables simultaneous processing of 32-channel data sampled at 25 kHz/channel with 8bit/sample resolution with less than 5 mW power consumption for all modes of operation (monitoring, compression and sensing) at

• Type: Journal
• Year: 2011
• Where: ICASSP
• Authors: Fei Zhang, Mehdi Aghagolzadeh, Karim G. Oweiss
• Keywords: Brain Machine Interface, ICASSP 2011, MW Power Consumption, Power Consumption, Signal Processing