Hardware acceleration of iterative image reconstruction for X-ray computed tomography

X-ray computed tomography (CT) images could be improved using iterative image reconstruction if the 3D conebeam forward- and back-projection computations can be accelerated significantly. We investigated the feasibility of a field-programmable gate array (FPGA) implementation of the separable footprint (SF) forward projector. A 16-bit fixed-point quantization introduces negligible numerical errors without affecting the perceptual image quality. The SF-based 3D cone-beam projector can be efficiently parallelized and its memory bandwidth reduced by exploiting projection geometry and data locality. We demonstrate a fully pipelined, 75-way parallel hardware architecture of the SF forward projector on a Xilinx Virtex-5 FPGA that can complete one forward projection of a 320×320×61 object over 3,625 views in 6.3 seconds.

• Type: Journal
• Year: 2011
• Where: ICASSP
• Authors: Jung Kuk Kim, Zhengya Zhang, Jeffrey A. Fessler
• Keywords: 16-bit Fixed-point Quantization, Field-programmable Gate Array, ICASSP 2011, SF Forward Projector, Signal Processing