Hardware accelerated visual attention algorithm

— We present a hardware-accelerated implementation of a bottom-up visual attention algorithm. This algorithm generates a multi-scale saliency map from differences in image intensity, color, presence of edges and presence of motion. The visual attention algorithm is computed on a custom-designed FPGA-based dataflow computer for general-purpose state-of-theart vision algorithms. The vision algorithm is accelerated by our hardware platform and reports ×4 speedup when compared to a standard laptop with a 2.26 GHz Intel Dual Core processor and for image sizes of 480 × 480 pixels. We developed a real time demo application capable of > 12 frames per second with the same size images. We also compared the results of the hardware implementation of the algorithm to the eye fixation points of different subjects on six video sequences. We find that our implementation achieves precisions of fixation predictions of up to 1/14th of the size of time video frames.

• Type: Journal
• Year: 2011
• Where: CISS
• Authors: Polina Akselrod, Faye Zhao, Ifigeneia Derekli, Clément Farabet, Berin Martini, Yann LeCun, Eugenio Culurciello
• Keywords: CISS 2011, Dual Core Processor, Information Technology, Intel Dual Core Processor, Vision Algorithm