FPGA design and implementation for vertex extraction of polygonal shapes

This work focuses on developing systems of blocks in SIMULINK and VHDL to reuse on design of applications involving the recognition of polygonal objects. Usage of this work reduces time in the development of prototype solutions using FPGAs. The vertex extraction algorithm uses contour’s corners as the candidate set to select vertices by using local properties. SIMULINK and VHDL implementations were tested to be equal at I/O level. Using a Spartan 3E FPGA Starter kit for the hardware implementation probed that the VHDL implementation synthesizes. Binary images are loaded into the FPGA through a microSD memory card and the resulting data from the FPGA process is visualized through the Starter Kit built-in alphanumeric LCD. Test cases consider artificial cases to ensure wide case testing for case combination of the algorithm. These sets of components in software and hardware contribute by easing implementations on computer vision applications using polygons for object identification.

• Type: Journal
• Year: 2011
• Where: CONIELECOMP
• Authors: Jorge Martínez-Carballido, Jorge Guevara-Escobedo, Juan M. Ramirez-Cortes, Rubén Alejos Palomares
• Keywords: Communications, Computer Vision Applications, CONIELECOMP 2011, Vhdl Implementation, Vhdl Implementations