High-level synthesis of accelerators in embedded scalable platforms

cular, it raises the level of abstraction in the design process and guides designers in the application of high-level synthesis (HLS) tools. HLS enables a more efficient design of accelerators with a focus on their algorithmic properties, a broader exploration of their design space, and a more productive reuse across many different SoC projects.

• Type: Journal
• Year: 2016
• Where: ASPDAC
• Authors: Paolo Mantovani, Giuseppe Di Guglielmo, Luca P. Carloni
• Keywords: ASPDAC 2016, Hardware