Dynamic Memory Management in Vivado-HLS for Scalable Many-Accelerator Architectures

This paper discusses the incorporation of dynamic memory management during High-Level-Synthesis (HLS) for effective resource utilization in many-accelerator architectures targeting to FPGA devices. We show that in today’s FPGA devices, the main limiting factor of scaling the number of accelerators is the starvation of the available on-chip memory. For many-accelerator architectures, this leads in severe inefficiencies, i.e. memory-induced resource under-utilization of the rest of the FPGA’s resources. Recognizing that static memory allocation – the de-facto mechanism supported by modern design techniques and synthesis tools – forms the main source of “resource under-utilization” problems, we introduce the DMM-HLS framework that extends conventional HLS with dynamic memory allocation/deallocation mechanisms to be incorporated during many-accelerator synthesis. The proposed DMM-HLS framework enables each accelerator to dynamically adapt its allocated memory according to the...

• Type: Journal
• Year: 2015
• Where: ARC
• Authors: Dionysios Diamantopoulos, Sotirios Xydis, Kostas Siozios, Dimitrios Soudris
• Keywords: ARC 2015, Hardware