A low-radix and low-diameter 3D interconnection network design

Interconnection plays an important role in performance and power of CMP designs using deep sub-micron technology. The network-on-chip (NoCs) has been proposed as a scalable and high-bandwidth fabric for interconnect design. The advent of the 3D technology has provided further opportunity to reduce on-chip communication delay. However, the design of the 3D NoC topologies has important distinctions from 2D NoCs or off-chip interconnection networks. First, current 3D stacking technology allows only vertical inter-layer links. Hence, there cannot be direct connections between arbitrary nodes in different layers -- the vertical connection topology are essentially fixed. Second, the 3D NoC is highly constrained by the complexity and power of routers and links. Hence, low-radix routers are preferred over high-radix routers for lower power and better heat dissipation. This implies long network latency due to high hop counts in network paths. In this paper, we design a low-diameter 3D network ...

• Type: Conference
• Year: 2009
• Where: HPCA
• Authors: Bo Zhao, Jun Yang 0002, Xiuyi Zhou, Yi Xu, Youtao Zhang, Yu Du
• Keywords: Computer Architecture, HPCA 2009, Long Network Latency, Low-diameter 3D Network, Network Latency Reduction