A novel topology for Translinear (TL) loops comprising of CMOS Second Generation Current Conveyors (CC-II) and diodes is proposed. The proposed methodology opens a new paradigm towards the design of Static and Dynamic TL circuits in CMOS technology. Simulation of a current multiplier and a Log-domain integrator demonstrates the concept.
Debashis Dutta, Wouter A. Serdijn, Swapna Banerjee