Accurate and Complexity-Effective Spatial Pattern Prediction

Recent research suggests that there are large variations in a cache's spatial usage, both within and across programs. Unfortunately, conventional caches typically employ fixed cache line sizes to balance the exploitation of spatial and temporal locality, and to avoid prohibitive cache fill bandwidth demands. The resulting inability of conventional caches to exploit spatial variations leads to sub-optimal performance and unnecessary cache power dissipation. This paper describes the Spatial Pattern Predictor (SPP), a cost-effective hardware mechanism that accurately predicts reference patterns within a spatial group (i.e., a contiguous region of data in memory) at runtime. The key observation enabling an accurate, yet low-cost, SPP design is that spatial patterns correlate well with instruction addresses and data reference offsets within a cache line. We require only a small amount of predictor memory to store the predicted patterns. Simulation results for a 64-Kbyte 2way set-assoc...

• Type: Conference
• Year: 2004
• Where: HPCA
• Authors: Chi F. Chen, Se-Hyun Yang, Babak Falsafi, Andreas Moshovos
• Keywords: Cache Power Dissipation, Computer Architecture, HPCA 2004, Spatial Pattern Predictor, Spatial Patterns