Coping with The Variability of Combinational Logic Delays

Abstract— This paper proposes a technique for creating a combinational logic network with an output that signals when all other outputs have stabilized. The method is based on dual-rail encoding, and guarantees low timing overhead and reasonable area and power overhead. We discuss various scenarios in which completion detection can be used to measure the delay of a synchronous circuit at fabrication time or at run time, and of an asynchronous circuit at run time. We conclude by showing, on a large set of benchmarks, the effectiveness of the proposed technique.

• Type: Conference
• Year: 2004
• Where: ICCD
• Authors: Jordi Cortadella, Alex Kondratyev, Luciano Lavagno, Christos P. Sotiriou
• Keywords: Combinational Logic Network, Hardware, ICCD 2004, Low Timing Overhead, Run Time