Combined Channel Segmentation and Buffer Insertion for Routability and Performance Improvement of Field

In this paper, we propose a combined channel segmentation and buffer insertion approach, which minimizes the number of buffers inserted while satisfying the delay constraints for routing channels of fieldprogrammable analog arrays. A segmented routing algorithm based on minimum-cost-bipartite-matching is improved with demand awareness and used to evaluate the various routing channels generated. Experiments show that, compared to a sequential segmenting-then-buffering design, our approach can significantly reduce the total number of buffers required, while achieving improved routability and minimum average interconnect delay. It is also shown that by increasing the number of long segment appropriately, the algorithm can dramatically improve the routability with a moderate increase on the number of buffers.

• Type: Conference
• Year: 2004
• Where: ICCD
• Authors: Hu Huang, Joseph B. Bernstein, Martin Peckerar, Ji Luo
• Keywords: Average Interconnect Delay, Hardware, ICCD 2004, Segmented Routing Algorithm, Various Routing Channels