A High-Frequency Decimal Multiplier

Decimal arithmetic is regaining popularity in the computing community due to the growing importance of commercial, financial, and Internet-based applications, which process decimal data. This paper presents an iterative decimal multiplier, which is operates at high clock frequencies and scales well to large operand sizes. The multiplier uses a new decimal representation for intermediate products, which allows for a very fast twostage iterative multiplier design. Decimal multipliers, which are synthesized using a 0.11 micron CMOS standard cell library, operate at clock frequencies close to 2 GHz. The latency of the proposed design to multiply two n-digit BCD operands is (n + 8) cycles with a new multiplication able to begin every (n + 1) cycles.

• Type: Conference
• Year: 2004
• Where: ICCD
• Authors: Robert D. Kenney, Michael J. Schulte, Mark A. Erle
• Keywords: Decimal Multipliers, Hardware, ICCD 2004, Iterative Decimal Multiplier, Iterative Multiplier Design