The Size and Depth of Layered Boolean Circuits

We consider the relationship between size and depth for layered Boolean circuits, synchronous circuits and planar circuits as well as classes of circuits with small separators. In particular, we show that every layered Boolean circuit of size s can be simulated by a layered Boolean circuit of depth O( √ s log s). For planar circuits and synchronous circuits of size s, we obtain simulations of depth O( √ s). The best known result so far was by Paterson and Valiant [16], and Dymond and Tompa [6], which holds for general Boolean circuits and states that D(f) = O(C(f)/ log C(f)), where C(f) and D(f) are the minimum size and depth, respectively, of Boolean circuits computing f. The proof of our main result uses an adaptive strategy based on the two-person pebble game introduced by Dymond and Tompa [6]. Improving any of our results by polylog factors would immediately improve the bounds for general circuits. Key words: Boolean circuits, circuit size, circuit depth, pebble games

• Type: Conference
• Year: 2010
• Where: LATIN
• Authors: Anna Gál, Jing-Tang Jang
• Keywords: Boolean Circuits, Information Retrieval, LATIN 2010, Layered Boolean Circuit, Planar Circuits