Analysis of the TRIPS prototype block predictor

This paper analyzes the performance of the TRIPS prototype chip’s block predictor. The prototype is the first implementation of the block-atomic TRIPS architecture, wherein the unit of execution is a TRIPS hyperblock. The TRIPS prototype predictor uses a two-step prediction process: it first predicts the exit from the current hyperblock and uses the predicted exit in conjunction with the current hyperblock’s address to predict the next hyperblock. SPECint2000 and SPECfp2000 benchmarks record av

• Type: Conference
• Year: 2009
• Where: ISPASS
• Authors: Nitya Ranganathan, Doug Burger, Stephen W. Keckler
• Keywords: Block-atomic Trips Architecture, ISPASS 2009, Software Engineering, TRIPS Prototype Chip, TRIPS Prototype Predictor