GARNET: A detailed on-chip network model inside a full-system simulator

Until very recently, microprocessor designs were computation-centric. On-chip communication was frequently ignored. This was because of fast, single-cycle on-chip communication. The interconnect power was also insignificant compared to the transistor power. With uniprocessor designs providing diminishing returns and the advent of chip multiprocessors (CMPs) in mainstream systems, the on-chip network that connects different processing cores has become a critical part of the design. Transistor miniaturization has led to high global wire delay, and interconnect power comparable to transistor power. CMP design proposals can no longer ignore the interaction between the memory hierarchy and the interconnection network that connects various elements. This necessitates a detailed and accurate interconnection network model within a full-system evaluation framework. Ignoring the interconnect details might lead to inaccurate results when simulating a CMP architecture. It also becomes important t...

• Type: Conference
• Year: 2009
• Where: ISPASS
• Authors: Niket Agarwal, Tushar Krishna, Li-Shiuan Peh, Niraj K. Jha
• Keywords: Interconnection Network, Interconnection Network Model, ISPASS 2009, On-chip Communication, Software Engineering