A case for integrated processor-cache partitioning in chip multiprocessors

Existing cache partitioning schemes are designed in a manner oblivious to the implicit processor partitioning enforced by the operating system. This paper examines an operating system directed integrated processor-cache partitioning scheme that partitions both the available processors and the shared cache in a chip multiprocessor among different multi-threaded applications. Extensive simulations using a set of multiprogrammed workloads show that our integrated processor-cache partitioning scheme facilitates achieving better performance isolation as compared to state of the art hardware/software based solutions. Specifically, our integrated processor-cache partitioning approach performs, on an average, 20.83% and 14.14% better than equal partitioning and the implicit partitioning enforced by the underlying operating system, respectively, on the fair speedup metric on an 8 core system. We also compare our approach to processor partitioning alone and a state-of-the-art cache partitioni...

• Type: Conference
• Year: 2009
• Where: SC
• Authors: Shekhar Srikantaiah, Reetuparna Das, Asit K. Mishra, Chita R. Das, Mahmut T. Kandemir
• Keywords: Applied Computing, Cache Partitioning Scheme, Integrated Processor-cache Partitioning, Partitioning Scheme, SC 2009