An on-chip interconnect and protocol stack for multiple communication paradigms and programming models

A growing number of applications, with diverse requirements, are integrated on the same System on Chip (SoC) in the form of hardware and software Intellectual Property (IP). The diverse requirements, coupled with the IPs being developed by unrelated design teams, lead to multiple communication paradigms, programming models, and interface protocols that the on-chip interconnect must accommodate. Traditionally, on-chip buses offer distributed shared memory communication with established memory-consistency models, but are tightly coupled to a specific interface protocol. On-chip networks, on the other hand, offer layering and interface abstraction, but are centred around point-topoint streaming communication, and do not address issues at the higher layers in the protocol stack, such as memoryconsistency models and message-dependent deadlock. In this work we introduce an on-chip interconnect and protocol stack that combines streaming and distributed shared memory communication. The pro...

• Type: Conference
• Year: 2009
• Where: CODES
• Authors: Andreas Hansson, Kees Goossens
• Keywords: CODES 2009, Hardware-Software Codesign, Multiple Communication Paradigms, On-chip Interconnect, Protocol Stack