Accelerating Quadrature Methods for Option Valuation

This paper presents an architecture for FPGA acceleration of quadrature methods used for pricing complex options, such as discrete barrier, Bermudan, and American options. The architecture can be optimized for speed and power consumption by exploiting pipelining and parallelism to produce efficient implementations in reconfigurable logic. An optimised implementation using Graphics Processing Units (GPUs) is also developed, to provide a performance and efficiency comparison with an FPGA accelerator. Our 100MHz FPGA implementation demonstrates a 32.8 times speedup over a software implementation running on a Pentium 4 3.6GHz processor, and is 8.3 times more power efficient than a Tesla C1060 GPU with

• Type: Conference
• Year: 2009
• Where: FCCM
• Authors: Anson H. T. Tse, David B. Thomas, Wayne Luk
• Keywords: FCCM 2009, FPGA Acceleration, FPGA Accelerator, FPGA Implementation, Hardware