Abstract. Memory access latency can limit microcontroller system performance. SDRAM access control policies impact latency through SDRAM device state. It is shown that execution time can be reduced by using a state machine which predicts, for each access, the policy which will minimize latency. Two-level dynamic predictors are incorporated into the SDRAM controller. A range of organizations for dynamic predictors are described, and the performance improvements predicted by simulation are compared using execution time and prediction accuracy as metrics. Results show that pre
Ying Xu, Aabhas S. Agarwal, Brian T. Davis