Nanometer MOSFET effects on the minimum-energy point of 45nm subthreshold logic

In this paper, we observe that minimum energy Emin of subthreshold logic dramatically increases when reaching 45 nm node. We demonstrate by circuit simulation and analytical modeling that this increase comes from the combined effects of variability, gate leakage and DIBL. We then investigate the new impact of MOSFET parameters on Emin in nanometer technologies. We finally propose an optimum MOSFET selection intended for subthreshold circuit designers, which favors low-Vt mid-Lg devices in standard 45nm GP technology. The use of such optimum MOSFETs yields 35% Emin reduction for a benchmark multiplier with good speed performances and negligible area overhead. Categories and Subject Descriptors B.7.1 [Hardware]: Advanced technologies; D.8.2 [Hardware]: Performance Analysis and Design Aids. General Terms Design, performance. Keywords CMOS digital integrated circuits, gate leakage, short-channel effects, subthreshold logic, ultra-low power, variability.

• Type: Conference
• Year: 2009
• Where: ISLPED
• Authors: David Bol, Dina Kamel, Denis Flandre, Jean-Didier Legat
• Keywords: Gate Leakage, Hardware, ISLPED 2009, Minimum Energy Emin, Optimum Mosfets