A high-performance low-power nanophotonic on-chip network

On-chip communication, including short, often-multicast, latency-critical coherence and synchronization messages, and long, unicast, throughput-sensitive data transfer, limits the power efficiency and performance scalability of many-core chip-multiprocessor systems. This article presents Iris, a CMOS-compatible high-performance low-power nanophotonic on-chip network. Iris’ linear-waveguide-based throughputoptimized circuit-switched subnetwork supports throughputsensitive data transfer. Iris’ planar-waveguide-based WDM broadcast–multicast subnetwork optimizes latency-critical traffic and supports the circuit setup of circuit-switched communication. Overall, the proposed design delivers an on-chip communication backplane with high power efficiency, low latency, and excellent throughput. Categories and Subject Descriptors

• Type: Conference
• Year: 2009
• Where: ISLPED
• Authors: Zheng Li, Jie Wu, Li Shang, Alan R. Mickelson, Manish Vachharajani, Dejan Filipovic, Wounjhang Park, Yihe Sun
• Keywords: Hardware, ISLPED 2009, Nanophotonic On-chip Network, On-chip Communication, On-chip Communication Backplane