Speculative DMA for architecturally visible storage in instruction set extensions

Instruction set extensions (ISEs) can accelerate embedded processor performance. Many algorithms for ISE generation have shown good potential; some of them have recently been expanded to include Architecturally Visible Storage (AVS)—compiler-controlled memories, similar to scratchpads, that are accessible only to ISEs. To achieve a speedup using AVS, Direct Memory Access (DMA) transfers are required to move data from the main memory to the AVS; unfortunately, this creates coherence problems between the AVS and the cache, which previous methods for ISEs with AVS failed to address; additionally, these methods need to leave many conservative DMA transfers in place, whose execution significantly limits the achievable speedup. This paper presents a memory coherence scheme for ISEs with AVS, which can ensure execution correctness and memory consistency with minimal area overhead. We also present a method that speculatively removes redundant DMA transfers. Cycle-accurate experimental resu...

• Type: Conference
• Year: 2008
• Where: CODES
• Authors: Theo Kluter, Philip Brisk, Paolo Ienne, Edoardo Charbon
• Keywords: CODES 2008, Direct Memory Access, DMA Transfers, Hardware-Software Codesign, Instruction Set Extensions