Accurate models for estimating area and power of FPGA implementations

This paper presents accurate area and power estimation models for implementations using FPGAs from the Xilinx Virtex-2Pro family. These models are designed to facilitate efficient design space exploration in an automated algorithm-architecture codesign framework. Detailed models for accurately estimating the number of slices, block RAMs and 18x18-bit multipliers for fixed point and floating-point IP cores have been developed. These models are also utilized to develop accurate power models that consider the effect of logic power, signal power, clock power and I/O power. In all cases, the model coefficients have been derived by using curve fitting or regression analysis. The modeling error for the IP cores is very small (average 0.95%). The error for fairly large examples such as floating point

• Type: Conference
• Year: 2008
• Where: ICASSP
• Authors: Lanping Deng, Kanwaldeep Sobti, Chaitali Chakrabarti
• Keywords: Accurate Power Models, ICASSP 2008, IP Cores, Power Estimation Models, Signal Processing