Multi-optimization power management for chip multiprocessors

The emergence of power as a first-class design constraint has fueled the proposal of a growing number of run-time power optimizations. Many of these optimizations trade-off power saving opportunity for a variable performance loss which depends on application characteristics and program phase. Furthermore, the potential benefits of these optimizations are sometimes non-additive, and it can be difficult to identify which combinations of these optimizations to apply. Trial-and-error approaches have been proposed to adaptively tune a processor. However, in a chip multiprocessor, the cost of individually configuring each core under a wide range of optimizations would be prohibitive under simple trial-and-error approaches. In this work, we introduce an adaptive, multi-optimization power saving strategy for multi-core power management. Specifically, we solve the problem of meeting a global chip-wide power budget through run-time adaptation of highly configurable processor cores. Our ap...

• Type: Conference
• Year: 2008
• Where: IEEEPACT
• Authors: Ke Meng, Russ Joseph, Robert P. Dick, Li Shang
• Keywords: Hardware, IEEEPACT 2008, Optimizations Trade-off Power, Power Saving, Run-time Power Optimizations