Skewed redundancy

Technology scaling in integrated circuits has consistently provided dramatic performance improvements in modern microprocessors. However, increasing device counts and decreasing onchip voltage levels have made transient errors a first-order design constraint that can no longer be ignored. Several proposals have provided fault detection and tolerance through redundantly executing a program on an additional hardware thread or core. While such techniques can provide high fault coverage, they at best provide equivalent performance to the original execution and at worst incur a slowdown due to error checking, contention for shared resources, and synchronization overheads. This work achieves a similar goal of detecting transient errors by redundantly executing a program on an additional processor core, however it speeds up (rather than slows down) program execution compared to the unprotected baseline case. It makes the observation that a small number of instructions are detrimental to over...

• Type: Conference
• Year: 2008
• Where: IEEEPACT
• Authors: Gordon B. Bell, Mikko H. Lipasti
• Keywords: Dramatic Performance Improvements, Hardware, IEEEPACT 2008, Provide Equivalent Performance, Transient Errors