Accelerating multi-core processor design space evaluation using automatic multi-threaded workload synthesis

The design and evaluation of microprocessor architectures is a difficult and time-consuming task. Although small, handcoded microbenchmarks can be used to accelerate performance evaluation, these programs lack the complexity to stress increasingly complex architecture designs. Larger and more complex real-world workloads should be employed to measure the performance of a given design or to evaluate the efficiency of various design alternatives. These applications can take days or weeks if run to completion on a detailed architecture simulator. In the past, researchers have applied machine learning and statistical sampling methods to reduce the average number of instructions required for detailed simulation. Others have proposed statistical simulation and workload synthesis techniques, which can produce programs that emulate the execution characteristics of the application from which they are derived but have a much shorter execution period than the original. However, these existing me...

• Type: Conference
• Year: 2008
• Where: IISWC
• Authors: Clay Hughes, Tao Li
• Keywords: Architecture Design, Complex Real-world Workloads, IISWC 2008, Operating Systems, Workload Synthesis