Wafer-scale integration of analog neural networks

Abstract— This paper introduces a novel design of an artificial neural network tailored for wafer-scale integration. The presented VLSI implementation includes continuous-time analog neurons with up to 16k inputs. A novel interconnection and routing scheme allows the mapping of a multitude of network models derived from biology on the VLSI neural network while maintaining a high resource usage. A single 20 cm wafer contains about 60 million synapses. The implemented neurons are highly accelerated compared to biological real time. The power consumption of the dense interconnection network providing the necessary communication bandwidth is a critical aspect of the system integration. A novel asynchronous lowvoltage signaling scheme is presented that makes the wafer-scale approach feasible by limiting the total power consumption while simultaneously providing a flexible, programmable network topology.

• Type: Conference
• Year: 2008
• Where: IJCNN
• Authors: Johannes Schemmel, Johannes Fieres, Karlheinz Meier
• Keywords: Artificial Intelligence, Artificial Neural Network, IJCNN 2008, Neural Network, VLSI Neural Network