Beyond TCAMs: An SRAM-Based Parallel Multi-Pipeline Architecture for Terabit IP Lookup

—Continuous growth in network link rates poses a strong demand on high speed IP lookup engines. While Ternary Content Addressable Memory (TCAM) based solutions serve most of today’s high-end routers, they do not scale well for the next-generation [1]. On the other hand, pipelined SRAMbased algorithmic solutions become attractive. Intuitively multiple pipelines can be utilized in parallel to have a multiplicative effect on the throughput. However, several challenges must be addressed for such solutions to realize high throughput. First, the memory distribution across different stages of each pipeline as well as across different pipelines must be balanced. Second, the traffic on various pipelines should be balanced. In this paper, we propose a parallel SRAM-based multipipeline architecture for terabit IP lookup. To balance the memory requirement over the stages, a two-level mapping scheme is presented. By trie partitioning and subtrie-to-pipeline mapping, we ensure that each pipelin...

• Type: Conference
• Year: 2008
• Where: INFOCOM
• Authors: Weirong Jiang, Qingbo Wang, Viktor K. Prasanna
• Keywords: Communications, Content Addressable Memory, INFOCOM 2008, IP Lookup, IP Lookup Engines