Energy efficient packet classification hardware accelerator

Packet classification is an important function in a router’s line-card. Although many excellent solutions have been proposed in the past, implementing high speed packet classification reaching up to OC-192 and even OC-768 with reduced cost and low power consumption remains a challenge. In this paper, the HiCut and HyperCut algorithms are modified making them more energy efficient and better suited for hardware acceleration. The hardware accelerator has been tested on large rulesets containing up to 25,000 rules, classifying up to 77 Million packets per second (Mpps) on a Virtex5SX95T FPGA and 226 Mpps using 65nm ASIC technology. Simulation results show that our hardware accelerator consumes up to 7,773 times less energy compared with the unmodified algorithms running on a StrongARM SA-1100 processor when classifying packets. Simulation results also indicate ASIC implementation of our hardware accelerator can reach OC768 throughput with less power consumption than TCAM solutions.

• Type: Conference
• Year: 2008
• Where: IPPS
• Authors: Alan Kennedy, Xiaojun Wang, Bin Liu
• Keywords: Distributed And Parallel Computing, Hardware Accelerator, IPPS 2008, Packet Classification, Power Consumption