High-performance ASIC implementations of the 128-bit block cipher CLEFIA

— In the present paper, we introduce high-performance hardware architectures for the 128-bit block cipher CLEFIA and evaluate their ASIC performances in comparison with the ISO/IEC 18033-3 standard block ciphers (AES, Camellia, SEED, CAST-128, MISTY1, and TDEA). We designed five types of hardware architectures for CLEFIA, combining two loop structures and three F-functions. These designs were synthesized with a 90-nm CMOS standard cell library, and size and speed performances were evaluated. The highest hardware efficiency (defined as throughput/gates) obtained was 400.96 Kbps/gates,

• Type: Conference
• Year: 2008
• Where: ISCAS
• Authors: Takeshi Sugawara, Naofumi Homma, Takafumi Aoki, Akashi Satoh
• Keywords: 128-bit Block Cipher, Block Ciphers, Hardware, Hardware Architectures, ISCAS 2008