Power optimization of weighted bit-product summation tree for elementary function generator

— In this paper we propose a method for lowering the power consumption in our previously proposed method for approximating elementary functions. By rearranging the interconnect ordering in the summation tree we show that it is possible to lower the power consumption in the range of 6% to 34% compared to a random ordering. The reduction tree is progressively designed and the interconnect ordering is decided based on the transition activities of the partial products. The reduction in power consumption comes with no overhead in performance or area compared to the random ordering.

• Type: Conference
• Year: 2008
• Where: ISCAS
• Authors: Saeeid Tahmasbi Oskuii, Kenny Johansson, Oscar Gustafsson, Per Gunnar Kjeldsberg
• Keywords: Hardware, Interconnect Ordering, ISCAS 2008, Power Consumption, Random Ordering