Asynchronous balanced gates tolerant to interconnect variability

Abstract— Existing methods of gate level power attack countermeasures depend on exact capacitance matching of the dual-rail data outputs of each gate. Process variability and a lack of design tools make this requirement very difficult to satisfy in practice. We present a novel asynchronous dual-rail gate design which is power balanced and capable of tolerating interconnect variability. Additionally, its asynchronous nature allows for further tolerance to timing constraints and the asynchronous operation simplify secure, power balanced design.

• Type: Conference
• Year: 2008
• Where: ISCAS
• Authors: Konrad J. Kulikowski, Vyas Venkataraman, Zhen Wang, Alexander Taubin, Mark G. Karpovsky
• Keywords: Asynchronous Dual-rail Gate, Gate Level Power, Hardware, ISCAS 2008, Power Balanced Design