FPGA Implementations of a Parallel Associative Processor with Multi-Comparand Multi-Search Operations

Multi–comparand associative processors are efficient in parallel processing of complex search problems that arise from many application areas including computational geometry, graph theory and list/matrix computations. In this paper we report new FPGA implementations of a multi– comparand multi–search associative processor. The architecture of the processor working in a combined bit– serial/bit–parallel word–parallel mode and its functions are described. Then, several implementations of associative processors in VHDL, using Xilinx Foundation ISE software and Digilent development boards with Xilinx FPGA devices are reported. Parameters of the implemented FPGA processors are presented and discussed.

• Type: Conference
• Year: 2008
• Where: ISPDC
• Authors: Zbigniew Kokosinski, Bartlomiej Malus
• Keywords: Associative Processors, Distributed And Parallel Computing, ISPDC 2008, Multi–comparand Associative Processors, Multi–search Associative Processor