Exploiting Narrow Accelerators with Data-Centric Subgraph Mapping

The demand for high performance has driven acyclic computation accelerators into extensive use in modern embedded and desktop architectures. Accelerators that are ideal from a software perspective, are difficult or impossible to integrate in many modern architectures, though, due to area and timing requirements. This reality is coupled with the observation that many application domains under-utilize accelerator hardware, because of the narrow data they operate on and the nature of their computation. In this work, we take advantage of these facts to design accelerators capable of executing in modern architectures by narrowing datapath width and reducing interconnect. Novel compiler techniques are developed in order to generate highquality code for the reduced-cost accelerators and prevent performance loss to the extent possible. First, data width profiling is used to statistically determine how wide program data will be at run time. This information is used by the subgraph mapping al...

• Type: Conference
• Year: 2007
• Where: CGO
• Authors: Amir Hormati, Nathan Clark, Scott A. Mahlke
• Keywords: Acyclic Computation Accelerators, CGO 2007, Modern Architectures, Software Engineering, Subgraph Mapping Algorithms