Sciweavers

ICC
2007
IEEE

Lowering Error Floor of LDPC Codes Using a Joint Row-Column Decoding Algorithm

14 years 5 months ago
Lowering Error Floor of LDPC Codes Using a Joint Row-Column Decoding Algorithm
Low-density parity-check codes using the beliefpropagation decoding algorithm tend to exhibit a high error floor in the bit error rate curves, when some problematic graphical structures, such as the so-called trapping sets, exist in the corresponding Tanner graph. This paper presents a joint row-column decoding algorithm to lower the error floor, in which the column processing is combined with the processing of each row. By gradually updating the pseudo-posterior probabilities of all bit nodes, the proposed algorithm minimizes the propagation of erroneous information from trapping sets into the whole graph. The simulation indicates that the proposed joint decoding algorithm improves the performance in the waterfall region and lowers the error floor. Implementation results into field programmable gate array (FPGA) devices indicate that the proposed joint decoder increases the decoding speed by a factor of eight, compared to the traditional decoder.
Zhiyong He, Sébastien Roy 0002, Paul Fortie
Added 03 Jun 2010
Updated 03 Jun 2010
Type Conference
Year 2007
Where ICC
Authors Zhiyong He, Sébastien Roy 0002, Paul Fortier
Comments (0)