Sciweavers

Free Online Productivity Tools i2Speak i2Symbol i2OCR iTex2Img iWeb2Print iWeb2Shot i2Type iPdf2Split iPdf2Merge i2Bopomofo i2Arabic i2Style i2Image i2PDF iLatex2Rtf Sci2ools

23

ICCAD
2007
IEEE

favoriteEmaildiscussreport

83views Hardware» more ICCAD 2007»

Unified adaptivity optimization of clock and logic signals

14 years 5 months ago

Unified adaptivity optimization of clock and logic signals

Download www.ece.mtu.edu

Shiyan Hu, Jiang Hu

Real-time Traffic

Hardware | ICCAD 2007 |

claim paper

Related Content

» A novel sequential circuit optimization with clock gating logic

» Clock network minimization methodology based on incremental placement

» 12 Power reduction by withinfunctionalblock finegrained adaptive dual supply voltage contr...

» Unified Challenges in NanoCMOS HighLevel Synthesis

» Signal Processing at 250 MHz Using HighPerformance FPGAs

» ActivityAware Registers Placement for Low Power Gated Clock Tree Construction

» A methodology to analyze power voltage drop and their effects on clock skewdelay in early ...

» Analog MultiTone Signaling for HighSpeed Backplane Electrical Links

» Exploring highspeed lowpower hybrid arithmetic units at scaled supply and adaptive clockst...

Post Info
More Details (n/a)

Added	03 Jun 2010
Updated	03 Jun 2010
Type	Conference
Year	2007
Where	ICCAD
Authors	Shiyan Hu, Jiang Hu

Comments (0)