A Flexible Heterogeneous Multi-Core Architecture

Multi-core processors naturally exploit thread-level parallelism (TLP). However, extracting instruction-level parallelism (ILP) from individual applications or threads is still a challenge as application mixes in this environment are nonuniform. Thus, multi-core processors should be flexible enough to provide high throughput for uniform parallel applications as well as high performance for more general workloads. Heterogeneous architectures are a first step in this direction, but partitioning remains static and only roughly fits application requirements. This paper proposes the Flexible Heterogeneous MultiCore processor (FMC), the first dynamic heterogeneous multi-core architecture capable of reconfiguring itself to fit application requirements without programmer intervention. The basic building block of this microarchitecture is a scalable, variable-size window microarchitecture that exploits the concept of Execution Locality to provide large-window capabilities. This allows to...

• Type: Conference
• Year: 2007
• Where: IEEEPACT
• Authors: Miquel Pericàs, Adrián Cristal, Francisco J. Cazorla, Ruben Gonzalez, Daniel A. Jiménez, Mateo Valero
• Keywords: Hardware, Heterogeneous Multi-core Architecture, Heterogeneous Multicore Processor, IEEEPACT 2007, Multi-core Processors