Optimizing the Fast Fourier Transform on a Multi-core Architecture

The rapid revolution in microprocessor chip architecture due to multicore technology is presenting unprecedented challenges to the application developers as well as system software designers: how to best exploit the parallelism potential due to such multi-core architectures ? In this paper, we report an in-depth study on such challenges based on our experience of optimizing the Fast Fourier Transform (FFT) on the IBM Cyclops-64 chip architecture - a large-scale multi-core chip architecture consisting 160 thread units, associated memory banks and an interconnection network that connect them together in a shared memory organization. We demonstrate how multi-core architectures like the C64 could be used to achieve a high performance implementation of FFT both in 1D and 2D cases. We analyze the optimization challenges and opportunities including problem decomposition, load balancing, work distribution, and data-reuse, together with the exploiting of the C64 architecture features such as t...

• Type: Conference
• Year: 2007
• Where: IPPS
• Authors: Long Chen, Ziang Hu, Junmin Lin, Guang R. Gao
• Keywords: Architecture, Chip Architecture, Distributed And Parallel Computing, IPPS 2007, Multi-core Architecture