Time-Predictable Task Preemption for Real-Time Systems with Direct-Mapped Instruction Cache

Modern processors used in embedded systems are becoming increasingly powerful, having features like caches and pipelines to speedup execution. While execution speed of embedded software is generally increasing, it becomes more and more complex to verify the correct temporal behavior of software, running on this high-end embedded computer systems. To achieve time-predictability the authors introduced a very rigid software execution model with distribution being realized based on the time-triggered communication model. In this paper we analyze the timepredictability of a preempting task-activation, running on a hardware with direct-mapped instruction caches. As one result we analyze why a task-preemption driven by a clock interrupt is not suitable to guarantee timepredictability. As a second result, we present a timepredictable task-preemption driven by an instruction counter.

• Type: Conference
• Year: 2007
• Where: ISORC
• Authors: Raimund Kirner, Peter P. Puschner
• Keywords: Correct Temporal Behavior, Direct-mapped Instruction Caches, ISORC 2007, Software Engineering, Software Execution Model