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25

DATE
2010
IEEE

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A 14 bit, 280 kS/s cyclic ADC with 100 dB SFDR

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A 14 bit, 280 kS/s cyclic ADC with 100 dB SFDR

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— This paper presents the design of a 14 bit, 280 kS/s

Thomas Froehlich, Vivek Sharma, Markus Bingesser

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Added	10 Jul 2010
Updated	10 Jul 2010
Type	Conference
Year	2010
Where	DATE
Authors	Thomas Froehlich, Vivek Sharma, Markus Bingesser

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