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DATE
2010
IEEE

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SCOC3: a space computer on a chip

14 years 5 months ago

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—This paper presents the definition of an integrated processor core ASIC named SCOC3 which is designed for space computers. It also presents the validation method that has led to...

Franck Koebel, Jean-François Coldefy

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Id	Views	Title	Status

1	263	SCOC3: a space computer on a chip	claim
2	261	Evaluation and design exploration of solar harvested-energy prediction algorithm	claim
3	204	Assertion-based verification of RTOS properties	claim
4	202	FlashPower: A detailed power model for NAND flash memory	claim
5	201	COTS-based applications in space avionics	claim
6	198	A 14 bit, 280 kS/s cyclic ADC with 100 dB SFDR	claim
7	197	Compilation of stream programs for multicore processors that incorporate scratchpad memories	claim
8	195	Cool MPSoC programming	claim
9	193	Coordinated resource optimization in behavioral synthesis	claim
10	192	PhoenixSim: A simulator for physical-layer analysis of chip-scale photonic interconnection networks	claim
11	190	AUTOSAR basic software for complex control units	claim
12	190	Ultra-high throughput string matching for Deep Packet Inspection	claim
13	188	Power-accuracy tradeoffs in human activity transition detection	claim
14	185	Fault diagnosis of analog circuits based on machine learning	claim
15	185	Adapting to adaptive testing	claim
16	184	Parallel subdivision surface rendering and animation on the Cell BE processor	claim
17	184	An analytical method for evaluating Network-on-Chip performance	claim
18	183	Multithreaded code from synchronous programs: Extracting independent threads for OpenMP	claim
19	183	Monolithically stackable hybrid FPGA	claim
20	183	Toward optimized code generation through model-based optimization	claim
21	182	Fault-based attack of RSA authentication	claim
22	182	DAGS: Distribution agnostic sequential Monte Carlo scheme for task execution time estimation	claim
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24	180	Integration, cooling and packaging issues for aerospace equipments	claim
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26	180	A reconfigurable cache memory with heterogeneous banks	claim
27	178	Circuit propagation delay estimation through multivariate regression-based modeling under spatio-temporal variability	claim
28	177	A High-Voltage Low-Power DC-DC buck regulator for automotive applications	claim
29	176	Timing modeling and analysis for AUTOSAR-based software development - a case study	claim
30	175	Challenges in the design of automotive software	claim
31	175	Approximate logic synthesis for error tolerant applications	claim
32	174	VAPRES: A Virtual Architecture for Partially Reconfigurable Embedded Systems	claim
33	174	An HVS-based Adaptive Computational Complexity Reduction Scheme for H.264/AVC video encoder using Prognostic Early Mode Exclusion	claim
34	173	Robust design of embedded systems	claim
35	171	Statistical static timing analysis using Markov chain Monte Carlo	claim
36	171	Automated bottleneck-driven design-space exploration of media processing systems	claim
37	171	Power consumption of logic circuits in ambipolar carbon nanotube technology	claim
38	171	Digital statistical analysis using VHDL	claim
39	170	Analytical model for TDDB-based performance degradation in combinational logic	claim
40	169	Design space exploration of a mesochronous link for cost-effective and flexible GALS NOCs	claim
41	168	A new placement algorithm for the mitigation of multiple cell upsets in SRAM-based FPGAs	claim
42	168	Formal verification of analog circuits in the presence of noise and process variation	claim
43	168	Verifying UML/OCL models using Boolean satisfiability	claim
44	166	A special-purpose compiler for look-up table and code generation for function evaluation	claim
45	166	From transistors to MEMS: Throughput-aware power gating in CMOS circuits	claim
46	166	GoldMine: Automatic assertion generation using data mining and static analysis	claim
47	166	Increasing PCM main memory lifetime	claim
48	165	Multiplexed redundant execution: A technique for efficient fault tolerance in chip multiprocessors	claim
49	165	Multicore soft error rate stabilization using adaptive dual modular redundancy	claim
50	164	On passivity of the super node algorithm for EM modeling of interconnect systems	claim
51	163	AgeSim: A simulation framework for evaluating the lifetime reliability of processor-based SoCs	claim
52	163	Optimizing equivalence checking for behavioral synthesis	claim
53	163	A methodology for the characterization of process variation in NoC links	claim
54	163	Efficient High-Level modeling in the networking domain	claim
55	163	Enhanced Q-learning algorithm for dynamic power management with performance constraint	claim
56	162	Error resilience of intra-die and inter-die communication with 3D spidergon STNoC	claim
57	161	BISD: Scan-based Built-In self-diagnosis	claim
58	161	Aging-resilient design of pipelined architectures using novel detection and correction circuits	claim
59	161	FPGA-based adaptive computing for correlated multi-stream processing	claim
60	160	IVF: Characterizing the vulnerability of microprocessor structures to intermittent faults	claim
61	160	Soft error-aware design optimization of low power and time-constrained embedded systems	claim
62	159	A rapid prototyping system for error-resilient multi-processor systems-on-chip	claim
63	158	Ultra low-power 12-bit SAR ADC for RFID applications	claim
64	158	Energy- and endurance-aware design of phase change memory caches	claim
65	157	RMOT: Recursion in model order for task execution time estimation in a software pipeline	claim
66	157	An 11.6-19.3mW 0.375-13.6GHz CMOS frequency synthesizer with rail-to-rail operation	claim
67	156	Domain specific architecture for next generation wireless communication	claim
68	156	Spintronic memristor devices and application	claim
69	156	3D-integration of silicon devices: A key technology for sophisticated products	claim
70	156	Non-intrusive virtualization management using libvirt	claim
71	156	Defect aware X-filling for low-power scan testing	claim
72	155	A Smart Space application to dynamically relate medical and environmental information	claim
73	155	Scheduling and energy-distortion tradeoffs with operational refinement of image processing	claim
74	155	Bitstream processing for embedded systems using C++ metaprogramming	claim
75	154	ERSA: Error Resilient System Architecture for probabilistic applications	claim
76	154	A method to remove deadlocks in Networks-on-Chips with Wormhole flow control	claim
77	154	Computing robustness of FlexRay schedules to uncertainties in design parameters	claim
78	154	A proposal for real-time interfaces in SPEEDS	claim
79	153	Taming the component timing: A CBD methodology for real-time embedded systems	claim
80	153	Recursion-driven parallel code generation for multi-core platforms	claim
81	153	HORUS - high-dimensional Model Order Reduction via low moment-matching upgraded sampling	claim
82	153	Energy-efficient task allocation and scheduling for multi-mode MPSoCs under lifetime reliability constraint	claim
83	153	Heterogeneous vs homogeneous MPSoC approaches for a Mobile LTE modem	claim
84	152	Passive reduced order modeling of multiport interconnects via semidefinite programming	claim
85	151	A GPU based implementation of Center-Surround Distribution Distance for feature extraction and matching	claim
86	151	Analog circuit test based on a digital signature	claim
87	150	A memory- and time-efficient on-chip TCAM minimizer for IP lookup	claim
88	149	Integrated end-to-end timing analysis of networked AUTOSAR-compliant systems	claim
89	149	DynAHeal: Dynamic energy efficient task assignment for wireless healthcare systems	claim
90	149	Efficient decision ordering techniques for SAT-based test generation	claim
91	148	Intent-leveraged optimization of analog circuits via homotopy	claim
92	148	All things are connected	claim
93	148	DVFS based task scheduling in a harvesting WSN for Structural Health Monitoring	claim
94	148	Scalable stochastic processors	claim
95	148	Scoped identifiers for efficient bit aligned logging	claim
96	147	Detecting/preventing information leakage on the memory bus due to malicious hardware	claim
97	146	Leveraging application-level requirements in the design of a NoC for a 4G SoC - a case study	claim
98	146	Automatic pipelining from transactional datapath specifications	claim
99	145	An evaluation of a slice fault aware tool chain	claim
100	145	KL-Cuts: A new approach for logic synthesis targeting multiple output blocks	claim
101	145	Energy-efficient real-time task scheduling with temperature-dependent leakage	claim
102	144	A reconfigurable hardware for one bit transform based multiple reference frame Motion Estimation	claim
103	144	A robust ADC code hit counting technique	claim
104	142	Testing TSV-based three-dimensional stacked ICs	claim
105	142	A modeling method by eliminating execution traces for performance evaluation	claim
106	142	Automatic microarchitectural pipelining	claim
107	142	Transition-aware real-time task scheduling for reconfigurable embedded systems	claim
108	141	An embedded platform for privacy-friendly road charging applications	claim
109	141	Loosely Time-Triggered Architectures for Cyber-Physical Systems	claim
110	141	Carbon nanotube circuits: Living with imperfections and variations	claim
111	140	Variation-aware interconnect extraction using statistical moment preserving model order reduction	claim
112	140	Construction of dual mode components for reconfiguration aware high-level synthesis	claim
113	139	Constant-time admission control for Deadline Monotonic tasks	claim
114	139	Pareto efficient design for reconfigurable streaming applications on CPU/FPGAs	claim
115	139	Finding reset nondeterminism in RTL designs - scalable X-analysis methodology and case study	claim
116	139	A general mathematical model of probabilistic ripple-carry adders	claim
117	138	Checking and deriving module paths in Verilog cell library descriptions	claim
118	138	An efficient distributed memory interface for many-core platform with 3D stacked DRAM	claim
119	137	Deterministic, predictable and light-weight multithreading using PRET-C	claim
120	136	Reversible logic synthesis through ant colony optimization	claim
121	135	Mapping scientific applications on a large-scale data-path accelerator implemented by single-flux quantum (SFQ) circuits	claim
122	134	Simultaneous budget and buffer size computation for throughput-constrained task graphs	claim
123	134	Constrained Power Management: Application to a multimedia mobile platform	claim
124	134	Pseudo-CMOS: A novel design style for flexible electronics	claim
125	134	Layout-aware pseudo-functional testing for critical paths considering power supply noise effects	claim
126	134	Combining optimizations in automated low power design	claim
127	132	Programmable aging sensor for automotive safety-critical applications	claim
128	132	A systematic approach to the test of combined HW/SW systems	claim
129	132	Differential Power Analysis enhancement with statistical preprocessing	claim
130	131	Energy-performance design space exploration in SMT architectures exploiting selective load value predictions	claim
131	131	GentleCool: Cooling aware proactive workload scheduling in multi-machine systems	claim
132	131	Ultra-low power mixed-signal design platform using subthreshold source-coupled circuits	claim
133	131	Spinto: High-performance energy minimization in spin glasses	claim
134	130	Supporting Distributed Shared Memory on multi-core Network-on-Chips using a dual microcoded controller	claim
135	129	A power optimization method for CMOS Op-Amps using sub-space based geometric programming	claim
136	129	AUTOSAR and the automotive tool chain	claim
137	129	Block-level bayesian diagnosis of analogue electronic circuits	claim
138	127	A portable multi-pitch e-drum based on printed flexible pressure sensors	claim
139	127	A generalized control-flow-aware pattern recognition algorithm for behavioral synthesis	claim
140	127	Automatic generation of software TLM in multiple abstraction layers for efficient HW/SW co-simulation	claim
141	126	Leveraging dominators for preprocessing QBF	claim
142	126	Scenario-based analysis and synthesis of real-time systems using uppaal	claim
143	125	Scenario extraction for a refined timing-analysis of automotive network topologies	claim
144	125	pSHS: A scalable parallel software implementation of Montgomery multiplication for multicore systems	claim
145	124	On the construction of guaranteed passive macromodels for high-speed channels	claim
146	124	Reuse-aware modulo scheduling for stream processors	claim
147	124	Control network generator for latency insensitive designs	claim
148	124	Energy-efficient variable-flow liquid cooling in 3D stacked architectures	claim
149	123	Interconnect delay and slew metrics using the beta distribution	claim
150	123	Accelerating Lightpath setup via broadcasting in binary-tree waveguide in Optical NoCs	claim
151	122	SimTag: Exploiting tag bits similarity to improve the reliability of the data caches	claim
152	122	Equivalent circuit modeling of multilayered power/ground planes for fast transient simulation	claim
153	122	Optimal regulation of traffic flows in networks-on-chip	claim
154	122	Correlation controlled sampling for efficient variability analysis of analog circuits	claim
155	121	Tighter integration of BDDs and SMT for Predicate Abstraction	claim
156	121	Properties of and improvements to time-domain dynamic thermal analysis algorithms	claim
157	121	Cost modeling and cycle-accurate co-simulation of heterogeneous multiprocessor systems	claim
158	121	Using filesystem virtualization to avoid metadata bottlenecks	claim
159	120	Linear programming approach for performance-driven data aggregation in networks of embedded sensors	claim
160	120	UML design for dynamically reconfigurable multiprocessor embedded systems	claim
161	120	Memory testing with a RISC microcontroller	claim
162	119	Exploiting local logic structures to optimize multi-core SoC floorplanning	claim
163	119	Optimized self-tuning for circuit aging	claim
164	119	Practical Monte-Carlo based timing yield estimation of digital circuits	claim
165	118	Proactive NBTI mitigation for busy functional units in out-of-order microprocessors	claim
166	118	Exploiting multiple switch libraries in topology synthesis of on-chip interconnection network	claim
167	116	RTOS-aware refinement for TLM2.0-based HW/SW designs	claim
168	115	Power efficient voltage islanding for Systems-on-chip from a floorplanning perspective	claim
169	114	Efficient power conversion for ultra low voltage micro scale energy transducers	claim
170	113	PM-COSYN: PE and memory co-synthesis for MPSoCs	claim
171	111	Dynamically reconfigurable register file for a softcore VLIW processor	claim
172	111	Instruction precomputation with memoization for fault detection	claim
173	111	Evaluation of runtime task mapping heuristics with rSesame - a case study	claim
174	110	Enabling efficient post-silicon debug by clustering of hardware-assertions	claim
175	110	An RDL-configurable 3D memory tier to replace on-chip SRAM	claim
176	110	Multi-temperature testing for core-based system-on-chip	claim
177	109	TIMBER: Time borrowing and error relaying for online timing error resilience	claim
178	108	Performance-asymmetry-aware topology virtualization for defect-tolerant NoC-based many-core processors	claim
179	107	An error-correcting unordered code and hardware support for robust asynchronous global communication	claim
180	107	Worst case delay analysis for memory interference in multicore systems	claim
181	105	Modeling constructs and kernel for parallel simulation of accuracy adaptive TLMs	claim
182	104	Large-scale Boolean matching	claim
183	103	A compact digital amplitude modulator in 90nm CMOS	claim
184	98	SigNet: Network-on-chip filtering for coarse vector directories	claim
185	97	Run-time spatial resource management for real-time applications on heterogeneous MPSoCs	claim
186	95	A reconfigurable multiprocessor architecture for a reliable face recognition implementation	claim
187	89	Improved countermeasure against Address-bit DPA for ECC scalar multiplication	claim
188	76	Scalable codeword generation for coupled buses	claim

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