A 32-bit Decimal Floating-Point Logarithmic Converter

This paper presents a new design and implementation of a 32-bit decimal floating-point (DFP) logarithmic converter based on the digit-recurrence algorithm. The converter can calculate accurate logarithms of 32-bit DFP numbers which are defined in the IEEE 754-2008 standard. Redundant digit e1 is obtained by look-up table in the first iteration and the rest redundant digits ej are selected by rounding the scaled remainder during the succeeding iterations. The sequential architecture of the proposed 32-bit DFP logarithmic converter is implemented on Xilinx Virtex-II Pro P30 FPGA device and then synthesized with TMSC 0.18-um standard cell library. The implementation results indicate that the maximum frequency of the proposed architecture is 47.7 MHz in FPGA and 107.9 MHz in TMSC 0.18-um technology. The faithful 32-bit DFP logarithm results can be obtained in 18 cycles.

• Type: Conference
• Year: 2009
• Where: ARITH
• Authors: Dongdong Chen, Yu Zhang, Younhee Choi, Moon Ho Lee, Seok-Bum Ko
• Keywords: 32-bit Dfp, 32-bit Dfp Numbers, Applied Computing, ARITH 2009, DFP Logarithmic Converter