A 3d-audio reconfigurable processor

Various multimedia communication systems based on 3DAudio algorithms have been proposed by researchers from the acoustic data processing domain. However, all systems reported in the literature follow a PC-based approach that introduces processing bottlenecks and excessive power consumption. In order to alleviate these problems, we propose a reconfigurable 3D-Audio processor that can record and render sound sources concurrently. Audio recording and rendering are performed by two hardware accelerators exploiting the beamforming and the Wave Field Synthesis algorithms. The theoretical scalability of the proposed processor is explored with respect to systems consisting of different microphone and loudspeaker arrays configurations. A working FPGA prototype is compared against a software implementation on a Core2 Duo system. Results suggest that the proposed reconfigurable hardware solution can process data up to 2.4x faster than the software approach, while power consumption is approximate...

• Type: Conference
• Year: 2010
• Where: FPGA
• Authors: Dimitris Theodoropoulos, Georgi Kuzmanov, Georgi Gaydadjiev
• Keywords: Excessive Power Consumption, FPGA, FPGA 2010, Power Consumption, Reconfigurable 3D-Audio Processor