Programming Model and Low-level Language for a Coarse-Grained Reconfigurable Multimedia Processor

We present the architecture and programming model for MORA, a coarse-grained reconfigurable processor aimed at multimedia applications. The MORA architecure is a MIMD machine consisting of a 2-D array of reconfigurable cells (RC) with a flexible reconfigurable interconnect network. MORA is designed to support high-throughput data-parallel pipelined processing. We describe the design and implementation of the RC and present simulation results. Apart from its performance, the distinguishing feature of MORA is its design support for programmability. We present a novel assembly language, MORA assembly, which provides a low-level but flexible programming model for the architecture.

• Type: Journal
• Year: 2009
• Where: ERSA
• Authors: Wim Vanderbauwhede, Martin Margala, Sai Rahul Chalamalasetti, Sohan Purohit
• Keywords: Coarse-grained Reconfigurable Processor, ERSA 2009, Flexible Reconfigurable Interconnect, Hardware, MORA Architecure