A 52mW 1200MIPS compact DSP for multi-core media SoC

- This paper presents a DSP core for multi-core media SoC, which is optimized to execute a set of signal processing tasks very efficiently. The fully-programmable core has a data-centric instruction set and a corresponding latency-insensitive microarchitecture, where the hardware design is optimized concurrently with its automatic software generator. The proposed DSP core has 3X performance (in cycles) of those found in commercial dualcore application processors with similar computing resources. The silicon implementation in UMC 0.18µm 1P6M CMOS technology operates at 314MHz and consumes only 52mW average power.

• Type: Conference
• Year: 2006
• Where: ASPDAC
• Authors: Shih-Hao Ou, Tay-Jyi Lin, Chao-Wei Huang, Yu-Ting Kuo, Chie-Min Chao, Chih-Wei Liu, Chein-Wei Jen
• Keywords: ASPDAC 2006, Corresponding Latency-insensitive Microarchitecture, DSP Core, Multi-core Media Soc